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GTL2007
13-bit GTL to LVTTL translator with power good control
Rev. 01 -- 2 June 2005 Product data sheet
1. General description
The GTL2007 is a customized translator between dual Xeon processors, Platform Health Management, South Bridge and Power Supply LVTTL and GTL signals. The GTL2007 is derived from the GTL2006 with an enable function added that disables the error output to the monitoring agent for platforms that monitor the individual error conditions from each processor. This enable function can be used so that false error conditions are not passed to the monitoring agent when the system is unexpectedly powered down. This unexpected power-down could be from a power supply overload, a CPU thermal trip, or some other event of which the monitoring agent is unaware. A typical implementation would be to connect each enable line to the system power good signal or the individual enables to the VRD power good for each processor. The Nocona and Dempsey/Blackford Xeon processors specify a VTT of 1.2 V and 1.1 V, as well as a nominal Vref of 0.76 V and 0.73 V respectively. To allow for future voltage level changes that may extend Vref to 0.63 of VTT (minimum of 0.693 V with VTT of 1.1 V) the GTL2009 allows a minimum Vref of 0.66 V. Characterization results show that there is little DC or AC performance variation between these levels. The GTL2007 is the companion chip to the GTL2009 3-bit GTL Front-Side Bus frequency comparator that is used in dual-processor Xeon applications.
2. Features
s s s s s Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver 3.0 V to 3.6 V operation LVTTL I/O not 5 V tolerant Series termination on the LVTTL outputs of 30 ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 s Latch-up testing is done to JEDEC Standard JESD78 which exceeds 500 mA s Package offered: TSSOP28
Philips Semiconductors
GTL2007
13-bit GTL to LVTTL translator with power good control
3. Quick reference data
Table 1: Quick reference data Tamb = 25 C Symbol tPLH tPHL Cio Parameter propagation delay; An-to-Bn or Bn-to-An input/output capacitance; A-to-B input/output capacitance; B-to-A Conditions CL = 50 pF; VCC = 3.3 V outputs disabled; VI and VO = 0 V or 3.0 V Min Typ 5.5 5.5 2.0 1.5 Max 3.0 2.5 Unit ns ns pF pF
4. Ordering information
Table 2: Ordering information Tamb = -40 C to +85 C Type number GTL2007PW Topside mark GTL2007 Package Name TSSOP28 Description plastic thin shrink small outline package; 28 leads; body width 4.4 mm Version SOT361-1
Standard packing quantities and other packaging data are available at www.semiconductors.philips.com/standardics/packaging.
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Product data sheet
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Philips Semiconductors
GTL2007
13-bit GTL to LVTTL translator with power good control
5. Functional diagram
GTL2007
GTL VREF 1AO LVTTL outputs 2AO 3 26 2BI 1 2 27 1BI GTL inputs
5A LVTTL inputs/outputs (open-drain) 6A
4
25
7BO1 GTL outputs
5
24
7BO2
LVTTL input
EN1
6
23
EN2
LVTTL input
GTL input
11BI
7
22
11BO
GTL output
LVTTL input/output (open-drain)
11A
8
DELAY(1) 21 5BI
GTL input
9BI
9
DELAY(1) 20 6BI GTL inputs
3AO LVTTL outputs 4AO
10
19
3BI
11
18
4BI
10AI1 LVTTL inputs 10AI2
12
17
10BO1 GTL outputs
13
16
10BO2
15
9AO
LVTTL output
002aab210
(1) The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a LOW glitch on the 7BO1/7BO2 outputs.
Fig 1. Logic diagram of GTL2007
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GTL2007
13-bit GTL to LVTTL translator with power good control
6. Pinning information
6.1 Pinning
VREF 1AO 2AO 5A 6A EN1 11BI 11A 9BI
1 2 3 4 5 6 7 8 9
28 VCC 27 1BI 26 2BI 25 7BO1 24 7BO2 23 EN2 22 11BO 21 5BI 20 6BI 19 3BI 18 4BI 17 10BO1 16 10BO2 15 9AO
002aab209
GTL2007PW
3AO 10 4AO 11 10AI1 12 10AI2 13 GND 14
Fig 2. Pin configuration for TSSOP28
6.2 Pin description
Table 3: Symbol VREF 1AO 2AO 5A 6A EN1 11BI 11A 9BI 3AO 4AO 10AI1 10AI2 GND 9AO 10BO2 10BO1 4BI 3BI
9397 750 13264
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Description GTL reference voltage data output (LVTTL) data output (LVTTL) data input/output (LVTTL), open-drain data input/output (LVTTL), open-drain enable input (LVTTL) data input (GTL) data input/output (LVTTL), open-drain data input (GTL) data output (LVTTL) data output (LVTTL) data input (LVTTL) data input (LVTTL) ground (0 V) data output (LVTTL) data output (GTL) data output (GTL) data input (GTL) data input (GTL)
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Product data sheet
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Philips Semiconductors
GTL2007
13-bit GTL to LVTTL translator with power good control
Pin description ...continued Pin 20 21 22 23 24 25 26 27 28 Description data input (GTL) data input (GTL) data output (GTL) enable input (LVTTL) data output (GTL) data output (GTL) data input (GTL) data input (GTL) positive supply voltage
Table 3: Symbol 6BI 5BI 11BO EN2 7BO2 7BO1 2BI 1BI VCC
7. Functional description
Refer to Figure 1 "Logic diagram of GTL2007" on page 3.
7.1 Function tables
Table 4: GTL input signals H = HIGH voltage level; L = LOW voltage level. Input 1BI/2BI/3BI/4BI/9BI L H
[1]
Output [1] 1AO/2AO/3AO/4AO/9AO L H
1AO, 2AO, 3AO, 4AO and 5A/6A condition changed by ENn power good signal as described in Table 5 and Table 6.
Table 5: EN1 power good signal H = HIGH voltage level; L = LOW voltage level. EN1 L H 1AO and 2AO H follows BI 5A 5BI disconnected 5BI connected
Table 6: EN2 power good signal H = HIGH voltage level; L = LOW voltage level. EN2 L H 3AO and 4AO H follows BI 6A 6BI disconnected 6BI connected
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Product data sheet
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GTL2007
13-bit GTL to LVTTL translator with power good control
Table 7: SMI signals H = HIGH voltage level; L = LOW voltage level. Input 10AI1/10AI2 L L H H Input 9BI L H L H Output 10BO1/10BO2 L L L H
Table 8: PROCHOT signals H = HIGH voltage level; L = LOW voltage level. Input 5BI/6BI L H H
[1]
Input/output 5A/6A (open-drain) L L [2] H
Output 7BO1/7BO2 H [1] L H
The enable on 7BO1/7BO2 includes a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a low glitch on the 7BO1/7BO2 outputs. Open-drain input/output terminal is driven to logic LOW state by other driver.
[2]
Table 9: NMI signals H = HIGH voltage level; L = LOW voltage level. Input 11BI L L H
[1]
Input/output 11A (open-drain) H L [1] L
Output 11BO L H H
Open-drain input/output terminal is driven to logic LOW state by other driver.
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GTL2007
13-bit GTL to LVTTL translator with power good control
8. Application design-in information
VTT
56 R 56
VTT
VCC
1.5 k to 1.2 k 2R 1.5 k
PLATFORM HEALTH MANAGEMENT CPU1 1ERR_L CPU1 THRMTRIP L CPU1 PROCHOT L CPU2 PROCHOT L
VCC VREF 1AO 2AO 5A 6A EN1 11B1 VCC 1BI 2BI 7BO1 7BO2 EN2 11B0 CPU1 IERR_L THRMTRIP L FORCEPR_L PROCHOT L NMI CPU1 SMI L FORCEPR_L PROCHOT L IERR_L THRMTRIP L NMI CPU2 SMI L CPU2
GTL2007
NMI_L 11A 9BI CPU2 IERR_L CPU2 THRMTRIP L CPU1 SMI L CPU2 SMI L SMI_BUFF_L 3AO 4AO 10AI1 10AI2 GND 5BI 6BI 3BI 4BI 10BO1 10BO2 9AO
SOUTHBRIDGE NMI SOUTHBRIDGE SMI_L power supply POWER GOOD
002aab211
Fig 3. Typical application
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Product data sheet
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GTL2007
13-bit GTL to LVTTL translator with power good control
9. Limiting values
Table 10: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). [1] Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO Parameter DC supply voltage input clamping diode current DC input voltage output diode clamping current DC output voltage VI < 0 V A port (LVTTL) B port (GTL) VO < 0 V output in OFF or HIGH state; A port output in OFF or HIGH state; B port IOL IOH Tstg Tj(max)
[1]
Conditions
Min -0.5 -0.5 [3] -0.5 [3] -0.5 [3] -0.5 [3] -60
[2]
Max +4.6 -50 +4.6 +4.6 -50 +4.6 +4.6 32 30 -32 +150 +125
Unit V mA V V mA V V mA mA mA C C
current into any output in the LOW state
A port B port
current into any output in the HIGH state A port storage temperature maximum junction temperature
-
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Section 10 "Recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] [3]
10. Recommended operating conditions
Table 11: Symbol VCC VTT Vref VI VIH VIL IOH IOL Tamb Operating conditions Parameter supply voltage termination voltage reference voltage input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current ambient temperature GTL GTL A port B port A port and ENn B port A port and ENn B port A port A port B port operating in free-air Conditions Min 3.0 0.64 0 0 2 Vref + 0.050 -40 Typ 3.3 1.2 0.8 3.3 VTT Max 3.6 1.1 3.6 3.6 0.8 Vref - 0.050 -16 16 15 +85 Unit V V V V V V V V V mA mA mA C
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GTL2007
13-bit GTL to LVTTL translator with power good control
11. Static characteristics
Table 12: Static characteristics Recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = -40 C to +85 C Symbol VOH Parameter HIGH-level output voltage LOW-level output voltage Conditions A port; VCC = 3.0 V to 3.6 V; IOH = -100 A A port; VCC = 3.0 V; IOH = -16 mA VOL A port; VCC = 3.0 V; IOL = 4 mA A port; VCC = 3.0 V; IOL = 8 mA A port; VCC = 3.0 V; IOL = 16 mA B port; VCC = 3.0 V; IOL = 15 mA II input current A port; VCC = 3.6 V; VI = VCC A port; VCC = 3.6 V; VI = 0 V B port; VCC = 3.6 V; VI = VTT or GND ICC ICC [3] Cio supply current additional quiescent current (per input) input/output capacitance A or B port; VCC = 3.6 V; VI = VCC or GND; IO = 0 mA A port or control inputs; VCC = 3.6 V; VI = VCC - 0.6 V A port; VO = 3.0 V or 0 V B port; VO = VTT or 0 V
[2]
Min VCC - 0.2 2.1 -
Typ [1] 3.0 2.3 0.15 0.3 0.6 0.13 8 2.5 1.5
Max 0.4 0.55 0.8 0.4 1 1 1 12 500 3.5 2.5
Unit V V V V V V A A A mA A pF pF
[2] [2] [2] [2] [2]
[1] [2] [3]
All typical values are measured at VCC = 3.3 V and Tamb = 25 C. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. This is the increase in supply current for each input that is at the specified LVTTL voltage level rather than VCC or GND.
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Philips Semiconductors
GTL2007
13-bit GTL to LVTTL translator with power good control
12. Dynamic characteristics
Table 13: Dynamic characteristics VCC = 3.3 V 0.3 V Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLZ tPZL tPLH tPHL tPLH tPHL tPLZ tPZL
[2]
Parameter propagation delay, An to Bn propagation delay, nBI to nAO propagation delay, 9BI to 10BOn propagation delay, 11BI to 11BO disable time from LOW level, nBI to nA (I/O) enable time to LOW level, nBI to nA (I/O) propagation delay, 5BI to 7BO1 or 6BI to 7BO2 propagation delay, EN1 to nAO or EN2 to nAO disable time from LOW level, EN1 to 5A (I/O) or EN2 to 6A (I/O) enable time to LOW level, EN1 to 5A (I/O) or EN2 to 6A (I/O) propagation delay, An to Bn propagation delay, nBI to nAO propagation delay, 9BI to 10BOn propagation delay, 11BI to 11BO
Conditions see Figure 4 see Figure 5
Min 1 2 2 2 2 2 2 2
Typ [1] 4 5.5 5.5 5.5 6 6 8 14 13 12 7 205 6.5 6.5 3 7
Max 8 10 10 10 11 11 13 21 18 16 12 350 10 10 7 10
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Vref = 0.73 V; VTT = 1.1 V
see Figure 6
2 2
see Figure 7 see Figure 8 see Figure 9
4 100 2 2 1 2
Vref = 0.76 V; VTT = 1.2 V tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLZ tPZL tPLH tPHL
[2]
see Figure 4 see Figure 5
1 2 2 2 2 2 2 2
4 5.5 5.5 5.5 6 6 8 14 13 12 7 205
8 10 10 10 11 11 13 21 18 16 12 350
ns ns ns ns ns ns ns ns ns ns ns ns
disable time from LOW level, nBI to nA (I/O) enable time to LOW level, nBI to nA (I/O) propagation delay, 5BI to 7BO1 or 6BI to 7BO2
see Figure 6
2 2
see Figure 7
4 100
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GTL2007
13-bit GTL to LVTTL translator with power good control
Table 13: Dynamic characteristics ...continued VCC = 3.3 V 0.3 V Symbol tPLH tPHL tPLZ tPZL Parameter propagation delay, EN1 to nAO or EN2 to nAO disable time from LOW level, EN1 to 5A (I/O) or EN2 to 6A (I/O) enable time to LOW level, EN1 to 5A (I/O) or EN2 to 6A (I/O)
All typical values are at VCC = 3.3 V and Tamb = 25 C. Includes ~7.6 ns RC rise time of test load pull-up on 11A, 1.5 k pull-up and 21 pF load on 11A has about 23 ns RC rise time.
Conditions see Figure 8 see Figure 9
Min 2 2 1 2
Typ [1] 6.5 6.5 3 7
Max 10 10 7 10
Unit ns ns ns ns
[1] [2]
12.1 Waveforms
VM = 1.5 V at VCC 3.0 V for A ports; VM = Vref for B ports.
3.0 V input 1.5 V tPLH VH VM VM 0V
002aaa999 002aab000
1.5 V 0V tPHL VOH Vref Vref VOL
tpulse output
VM = 3.0 V for A port and VTT for B port
A port to B port
a. Pulse duration Fig 4. Voltage waveforms
b. Propagation delay times
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GTL2007
13-bit GTL to LVTTL translator with power good control
VTT input Vref tPLH output 1.5 V Vref
1/ V 3 TT
VTT input Vref tPZL Vref tPLZ
1/ V 3 TT
tPHL VOH 1.5 V VOL
002aab001
VCC output 1.5 V VOL + 0.3 V
002aab002
PRR 10 MHz; ZO = 50 ; tr 2.5 ns; tf 2.5 ns
Fig 5. Propagation delay, nBI to nAO
VTT input Vref tPLH Vref tPHL
1/ V 3 TT
Fig 6. nBI to nA (I/O)
3.0 V input 1.5 V tPLH 1.5 V 0V tPHL VOH output VOL 1.5 V 1.5 V VOL
002aab004
VOH/VTT output Vref Vref
002aab003
Fig 7. 5BI to 7BO or 6BI to 7BO2
Fig 8. EN1 to nAO or EN2 to nAO
3.0 V input 1.5 V tPLZ 1.5 V 0V tPZL VOH output VOL + 0.3 V 1.5 V VOL
002aab005
Fig 9. EN1 to 5A (I/O) or EN2 to 6A (I/O)
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GTL2007
13-bit GTL to LVTTL translator with power good control
13. Test information
VCC PULSE GENERATOR VI D.U.T.
RT CL 50 pF RL 500
VO
002aab006
Fig 10. Load circuit for A outputs
VTT VCC PULSE GENERATOR VI D.U.T.
RT CL 30 pF 50
VO
002aab264
Fig 11. Load circuit for B outputs
VCC VCC PULSE GENERATOR VI D.U.T.
RT CL 21 pF RL 1.5 k
VO
002aab265
Fig 12. Load circuit for open-drain LVTTL I/O
RL -- Load resistor CL -- Load capacitance; includes jig and probe capacitance RT -- Termination resistance; should be equal to ZOUT of pulse generators.
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GTL2007
13-bit GTL to LVTTL translator with power good control
14. Package outline
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1
D
E
A
X
c y HE vMA
Z
28
15
Q A2 pin 1 index A1 (A 3) A
Lp L detail X
1
e bp
14
wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 9.8 9.6 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.5 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT361-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 13. Package outline SOT361-1 (TSSOP28)
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GTL2007
13-bit GTL to LVTTL translator with power good control
15. Soldering
15.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
15.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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13-bit GTL to LVTTL translator with power good control
- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
15.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
15.5 Package related soldering information
Table 14: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
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Product data sheet
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Philips Semiconductors
GTL2007
13-bit GTL to LVTTL translator with power good control
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
16. Abbreviations
Table 15: Acronym CDM CMOS CPU ESD GTL HBM LVTTL MM PRR TTL VRD Abbreviations Description Charged Device Model Complementary Metal Oxide Silicon Central Processing Unit Electrostatic Discharge Gunning Transceiver Logic Human Body Model Low Voltage Transistor-Transistor Logic Machine Model Pulse Rate Repetition Transistor-Transistor Logic Voltage Regulator Down
17. Revision history
Table 16: Revision history Release date 20050602 Data sheet status Product data sheet Change notice Doc. number 9397 750 13264 Supersedes Document ID GTL2007_1
9397 750 13264
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 2 June 2005
17 of 19
Philips Semiconductors
GTL2007
13-bit GTL to LVTTL translator with power good control
18. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
19. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
21. Trademarks
Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners.
20. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
22. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 13264
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 2 June 2005
18 of 19
Philips Semiconductors
GTL2007
13-bit GTL to LVTTL translator with power good control
23. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 12.1 13 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18 19 20 21 22 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function tables . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application design-in information . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Test information . . . . . . . . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 16 Package related soldering information . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information . . . . . . . . . . . . . . . . . . . . 18
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 2 June 2005 Document number: 9397 750 13264
Published in The Netherlands

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